Synopsys Debuts Full-stack AI-based EDA Tool Suite for IC Engineers

At today’s Synopsys Users Group (SNUG) event, Synopsys has unveiled a full-stack suite of AI-based EDA tools.

There’s no doubt that artificial intelligence (AI) technology is becoming a topic that’s front and center in today’s world. And it’s not surprising that our engineering industry is way ahead of the game when it comes to incorporating AI into its tools.

Exemplifying that trend, today, at its annual Synopsys Users Group (SNUG) Silicon Valley Conference, Synopsys is announcing Synopsys.ai. The company describes Synopsys.ai as a suite of AI-driven tools for the design, verification, testing and manufacturing of advanced digital and analog chips.

Synopsys says the suite is intended to enable engineers to leverage AI using a cloud-based platform at every stage of chip design—including the system architecture definition stage, the design phase, and manufacturing.

AI-based EDA Addresses an Engineering Workload Problem

Explaining the broad problem that the Synopsys.ai addresses, Krishnamoorthy describes the demand for AI-based EDA in terms of an engineering workload gap as we enter a new era of semiconductor design.

“This is all about the productivity of VLSI design,” he says. “We are going from one generation to the next in terms of design complexity and process complexity. As a consequence of that, the total engineering effort that's needed to do a semiconductor design from one generation to the next has increased enormously.”

What this has created, says Krishnamoorthy, is a gap between the total amount of engineering needed to be done to create an IC and the total talent pool available to get it done. And the problem isn’t getting any better. He cites a report from Semiconductor Industry Association (SIA) by Boston Consulting Group saying that the U.S. semiconductor design industry may face a 23,000 shortfall of semiconductor engineers by 2030.

For EDA, an increased use of AI can help mitigate this gap. “This gives us a great opportunity to introduce a disruptive technology like AI to address that problem,” says Krishnamoorthy. “Our announcement today here at the SNUG conference is about how we have applied AI successfully across the entire EDA software stack—ranging from design to verification to test, and manufacturing.”

Building on DSO.ai With AI Tools for Verification and Test

The Synopsys.ai suite builds on the company’s earlier AI-based solution DSO.ai (Design Space Optimization AI), announced back in 2020. DSO.ai is an autonomous AI tool for IC design that searches for optimization targets in very large solution spaces of chip design. To date, DSO.ai has been adopted by 7 of the top 10 semiconductor firms across the globe and has scaled well past 100 commercial tape-outs. This offering is among others in the industry who have launched AI-based chip design efforts.

All About Circuits readers should mark their calendars for next Tuesday, April 4, because we will be airing our next Moore's Lobby podcast. The guest next Tuesday will be Stelios Diamantidis. He is a Distinguished Architect at Synopsys where he heads Synopsys' AI Solutions team in the Office of the President. In this role, Stelios oversees research on innovative machine-learning (ML) technology and its application to address systemic complexity in the design and manufacturing of integrated computational systems. In 2020, Stelios was the one who launched DSO.ai.

The Synopsys.ai tool suite announced today spans what the company calls a full stack of AI-based EDA solutions.

The Synopsys.ai EDA suite includes the following:

• Digital design space optimization ( DSO.ai) 
• Analog design automation
• Verification coverage closure and regression analysis
• Automated test generation
• Manufacturing solutions to speed development of lithography models to achieve the highest yield

Getting into more detail on the verification portion of Synopsys.ai, the suite includes VSO.ai (Verification Space Optimization AI), a tool designed to aid verification engineers in reaching coverage closure targets faster and finding more bugs. VSO.ai uses AI to examine the RTL to infer coverage. It also highlights areas where coverage is needed. This saves time for IC design engineers and ensures a high ROI on the tests, says the company.

On the test generation side, Synopsys.ai includes an AI-based automatic test pattern generation (ATPG) tool called TSO.ai (Test Space Optimization AI). Synopsys claims TSO.ai as “the industry’s first autonomous AI application for semiconductor test to minimize test cost and time-to-market for today's complex designs.”

TSO.ai works by automatically searching for an optimal solution in a large test search space. This is said to minimize pattern count and ATPG turn-around time, while also reducing test costs. Using AI also enables TSO.ai to provide automation, scalability, and expert level productivity that could not otherwise be accomplished manually.

More information about Synopsys.ai can be found in the company’s blog post today about the new suite.

Generative AI Not Now, But to Come

With generative AI technologies like ChatGPT so much in the news today, we asked Krishnamoorthy whether generative AI played any role in Synopsys.ai. He explained that generative AI is not what is going on in this particular case.

“When we talk about AI here, we are talking about a class of techniques that include things like reinforcement learning and other types of supervised and unsupervised learning,” he says. “Generative AI is really an exciting new area that we are looking at very closely. We think it's going to have a huge impact on our EDA business. An ability to automatically author System Verilog and the ability to author test benches—these are all dramatic productivity boosters.”

Krishnamoorthy also cited other capabilities, like supporting engineer customers in a more sophisticated way with AI chat bots. “We are studying it very closely,” he says. “We have a roadmap that includes incorporating many of these technologies in our portfolio as well.”