Drawing less than 120 mW and tolerating 30 krad of total ionizing dose, the chip-scale atomic clock keeps LEO satellites synchronized when GNSS timing is unavailable.
The new capacitors feature higher voltage ratings, improved thermal and vibration performance, and new safety qualifications for automotive and industrial applications.
The USC-run service that pioneered multi-project wafers in 1981 now offers a path from shared shuttle runs to full production on GlobalFoundries' FinFET and FD-SOI processes.
IBM leveraged its nanostack architecture, a technique that "builds a chip like a city," to pack nearly 100 billion transistors on a fingernail-sized chip.
The Korean unicorn packages four NPU dies with 144 GB of HBM3E and bets on an open software stack to serve large language models at lower cost per token.